library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity VGA_lecture_memoire is
  Port (
    CLK : in  STD_LOGIC;
    RST : in  STD_LOGIC;
    AD : out std_logic_vector(12 downto 0);
    D : in std_logic_vector(15 downto 0);
    R : out  STD_LOGIC;
    G : out  STD_LOGIC;
    B : out  STD_LOGIC;
    HS : out  STD_LOGIC;
    VS : out  STD_LOGIC
    );
end VGA_lecture_memoire;

architecture RTL of VGA_lecture_memoire is

  SIGNAL Xi, Xi_q: std_logic_vector(9 downto 0);
  SIGNAL Yi: std_logic_vector(8 downto 0);
  SIGNAL Pixel: std_logic;
  SIGNAL IMGi: std_logic;
  component VGA_gene_sync
    Port (
      CLK : in std_logic;
      HSYNC : out std_logic;
      VSYNC : out std_logic;
      IMG : out std_logic;
      X : out std_logic_vector(9 downto 0);
      Y : out std_logic_vector(8 downto 0)
      );
  end component;

 
 
begin

  C_GeneSync : VGA_gene_sync
    port map ( CLK => CLK, HSYNC=>HS,VSYNC=>VS,IMG=>IMGi,X=>Xi,Y=>Yi);
  -- A COMPLETER
 
  process(Xi, Yi)
  begin
        AD <= Yi(8 downto 1) & Xi(9 downto 5);
  end process;
 
  process(CLK)
  begin
    if (CLK'Event and CLK='1') then
        Xi_q <= Xi;
    end if;
  end process;
 
 
  process(D, Xi_q)
  begin
        --R <= IMGi and D(15 - CONV_Integer(Xi_q(4 downto 1)));
        G <= IMGi and D(15 - CONV_Integer(Xi_q(4 downto 1)));
        --B <= IMGi and D(15 - CONV_Integer(Xi_q(4 downto 1)));
  end process;
 
end RTL;